The scan based design is one of the most acceptable methods in the industry for testable design, and is mainly aimed in greatly reducing the complexity of the automatic test pattern generation (ATPG) process. When a scan chain includes too many scan elements, however, the required test time will be relatively long. Although the multiple scan chain design is one of measures which can effectively decrease the test time that the scan type circuit requires, the control circuit therefor normally is more complex than that for the single scan chain design and the required additional pin number will proportionally increase with the number of the scan chains.
S. Narayanan et al. disclosed in the article entitled “Asynchronous Multiple Scan Chains” for IEEE VLSI Test Symposium in 1995 that multiple scan chains are respectively grouped and the sequence of the schedule of test sessions is changed, in order to decrease the required test time, which, nevertheless, must be supported by multiple input/output lines.
In order to cope with the above situation, numerous modifications to the conventional multiple scan chain architecture were proposed. As an example, Z. Zhang et al. disclosed in the article entitled “An Efficient Multiple Scan Chain Testing Scheme” for Sixth Great Lakes Symposium on VLSI in 1996 cellular automata (CA) to serve as the required test pattern generator for tested circuits of different properties in order to overcome the linear dependency problem in test patterns. Since the control signal needs a multiplexer to select among the multiple scan chains, burdons on hardware and timing are increased.
For the present board level test, the boundary scan has become one of the compulsory test strategies. Since the present peripheral scan architecture only permits a data input line and a data output line, it cannot effectively support the multiple scan chain test design. This problem can be overcome by utilizing the demultiplexer to input the required test pattern from the single data line in time-division to respective scan chains, which can support the peripheral scan architecture but will increase the overall test time.